# define library paths in addition to /usr/lib # if I wanted to include libraries not in /usr/lib I'd specify # their path using -Lpath, something like: LFLAGS =
# define any directories containing header files other than /usr/include INCLUDES := $(patsubst %,-I%, $(INCLUDEDIRS:%/=%))
# define the C libs LIBS := $(patsubst %,-L%, $(LIBDIRS:%/=%))
# define the C source files SOURCES := $(wildcard $(patsubst %,%/*.cpp, $(SOURCEDIRS)))
# define the C object files OBJECTS := $(SOURCES:.cpp=.o)
# define the dependency output files DEPS := $(OBJECTS:.o=.d)
# # The following part of the makefile is generic; it can be used to # build any executable just by changing the definitions above and by # deleting dependencies appended to the file from 'make depend' #
# this is a suffix replacement rule for building .o's and .d's from .c's # it uses automatic variables $<: the name of the prerequisite of # the rule(a .c file) and $@: the name of the target of the rule (a .o file) # -MMD generates dependency output files same name as the .o file # (see the gnu make manual section about automatic variables) .cpp.o: $(CXX)$(CXXFLAGS)$(INCLUDES) -c -MMD $< -o $@
# define library paths in addition to /usr/lib # if I wanted to include libraries not in /usr/lib I'd specify # their path using -Lpath, something like: LFLAGS =
# define any directories containing header files other than /usr/include INCLUDES := $(patsubst %,-I%, $(INCLUDEDIRS:%/=%))
# define the C libs LIBS := $(patsubst %,-L%, $(LIBDIRS:%/=%))
# define the C source files SOURCES := $(wildcard $(patsubst %,%/*.cpp, $(SOURCEDIRS)))
# define the C object files OBJECTS := $(SOURCES:.cpp=.o)
# define the dependency output files DEPS := $(OBJECTS:.o=.d)
# # The following part of the makefile is generic; it can be used to # build any executable just by changing the definitions above and by # deleting dependencies appended to the file from 'make depend' #
# this is a suffix replacement rule for building .o's from .c's # it uses automatic variables $<: the name of the prerequisite of # the rule(a .c file) and $@: the name of the target of the rule (a .o file) # -MMD generates dependency output files same name as the .o file # (see the gnu make manual section about automatic variables) .cpp.o: $(CXX)$(CXXFLAGS)$(INCLUDES) -c -MMD $< -o $@